Referring to FIG. 1, there is shown a prior art charge-coupled device (CCD) as described in U.S. Pat. No. 6,462,779. This patent discloses a CCD 10 that may be either a linear CCD or an area array CCD. The CCD 10 is fabricated on a p-type well or substrate 12. If it is a well, then it may be a p-type well in an n-type substrate, a well-known configuration for interline-type CCD arrays. It also might be the substrate itself if it is a p-type substrate, a common configuration for full-frame or linear type CCD arrays. In the well or substrate 12, there is an n-type buried channel 14 which forms the charge packet 20 carrying layer. The buried channel 14 contains a channel adjustment implant 18 to alter the channel potential under the gates or a portion of the gates H1, H2, and H3. The gates are separated from the buried channel 14 by an electrically insulating gate dielectric 16. The CCD 10 as shown is referred to in the art as pseudo 2-phase architecture. The gates are clocked by three control signals H1, H2, and H3 to move the charge packet 20 through the CCD 10. The H3 signal goes to every other gate, and the gate signal between the H3 gates alternates between H1 and H2. FIG. 2 illustrates the voltages on the gates for normal speed full resolution charge transfer. The H1 and H2 gates are clocked with equal voltages and complimentary to H3. One half-clock cycle from time T0 to time T1 advances the charge packet 20 by one gate as shown in FIG. 1.
By altering the voltages applied to the gates as in FIG. 4 the function of the CCD 10 is altered. In this case, every other gate (H3) is held at a constant voltage while the gates on either side of H3, the H1 and H2 gates, are clocked in a complimentary manner. The result is shown in FIG. 3 where in one half clock cycle from time T0 to time T1 the charge packet 22 advances two gates. This transfers charge through the CCD at double the speed of the FIG. 2. timing.
The prior art is limited to two modes of operation, the first mode being normal speed charge transfer, and the second mode being double speed charge transfer. There are instances when it is desirable to transfer charge at an even faster rate than double speed mode. Such situations arise when it is desired to sum together three adjacent charge packets in a CCD for purposes of reducing the resolution of an image. For example, it is desirable to obtain 640 horizontal pixels at a faster frame rate from an area array that is normally 1920 horizontal pixels. By summing three pixels in a horizontal CCD a triple speed CCD would read out the line three times faster than the prior art.
Consequently, a need exists for a CCD that can read more than the currently available double speed transfer rate.